I applied through university. I interviewed at Apple in Sept 2017
Interview
This was an on campus interview for the position of design verification. They were looking for people skilled in verilog/vhdl, system verilog. It was a 30-minute interview. Simple Verilog questions and some questions on waveforms.
Interview questions [1]
Question 1
Q1. FIFO depth, given read and write rates for a burst of x writes
Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms)
Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms)
Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms)
Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms)
Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
There were 1 screening and 6 panel rounds and it was difficult especially UVM part also they AMBA protocols basic design questions like fsm fifo and all and more focus on constraints
Interview questions [1]
Question 1
UVM based questions and Assertions and constraints
I applied online. I interviewed at Apple (Sunnyvale, CA) in Mar 2026
Interview
I had a screening round that started directly without any introduction. I was asked questions about my resume, mainly about my projects. After that, I was given a coding question.
first asking about the tool experience, asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake , how do you deal with CDC problems, how to do the STA analysis, then final having a coding question
Interview questions [1]
Question 1
implementation of driver class based on the figure they gave