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      Cadence Design Systems

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      Verification Engineer Interview

      12 Oct 2018
      Anonymous interview candidate
      Pune
      No offer
      Negative experience
      Easy interview

      Application

      The process took 6 days. I interviewed at Cadence Design Systems (Pune)

      Interview

      This is regarding pune location which is tensilica group. During F2F i didn't feel its Cadence. During first round interviewer was asking previous projects and trying to understand what work have done along with some basic questions and if i stuck some were he was giving hints, second person was bit rude and was not interested at all during interview he was going outside, questions were simple though. like swapping and lot of arithmetic operations even i showed them using SV they want it again same thing in C or othey way which might be related to there work or somthing they want specific approch but his behaviour and way of talking was unprofessional that behaviour bounds to think me again to work in this culture and avoid questions.

      Interview questions [1]

      Question 1

      swaping in sv, c and lot of arithmetic operations and bit of uvm.
      Answer question

      Other Verification Engineer interview reviews for Cadence Design Systems

      Verification Engineer Interview

      16 Apr 2025
      Anonymous interview candidate
      New Delhi
      No offer
      Negative experience
      Average interview

      Application

      I applied through other source. The process took 1 week. I interviewed at Cadence Design Systems (New Delhi) in Apr 2025

      Interview

      Due to health issues, I was unwell during my scheduled interview and attempted to reschedule by reaching out to the HR contact I had. Unfortunately, I didn't receive a timely response and had to proceed with the interview while running a high fever. The panel showed little empathy, and the interaction lacked basic introductions or professionalism. Despite being asked moderate, relevant questions, I couldn’t perform at my best due to my condition and was later informed that the interview would not be rescheduled as the panel had decided to reject my profile.

      Interview questions [3]

      Question 1

      About scripting language python regex
      Answer question

      Question 2

      Basic digital circuits Counters and flip flops
      Answer question

      Question 3

      Factory overiding methods in UVM
      Answer question

      Verification Engineer Interview

      12 Oct 2024
      Anonymous employee
      Bengaluru
      Accepted offer
      Positive experience
      Average interview

      Application

      I applied through a staffing agency. The process took 2 days. I interviewed at Cadence Design Systems (Bengaluru) in Jun 2024

      Interview

      Smooth experience, in-depth questions asked on design , verification , scripting languages, computer architecture, linting, Verilog, SV, UVM etc The interviewers were sweet, there 3 rounds 2 technical one HR.

      Interview questions [1]

      Question 1

      Questions on Design flow, Verilog , SV etc
      Answer question

      Verification Engineer Interview

      21 Aug 2022
      Anonymous employee
      Accepted offer
      Positive experience
      Average interview

      Application

      I interviewed at Cadence Design Systems

      Interview

      An online test was conducted followed by a technical interview where technical questions from my resume were asked and an HR round. The final selection was announced after all the processes.

      Interview questions [1]

      Question 1

      About digital electronics and Verilog
      Answer question