# 84

Circuit Design Engineer interview questions shared by candidates

## Top Interview Questions

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Circuit Design Engineer was asked...26 May 2016

### Basic MOSFET, CMOS questions were asked.

Hey, you should feel glad that you weren't accepted by them. This company is very cheap and doesn't treat its employees well. Less

I guess...but it is not the right way to interview candidates don't you think?

That's really sad. They should rather go with Skype or any other means to interview. Now,. I have got an on-site call for Digital circuit design and I am giving it a serious thought 🤔 Less

### How Sense Amplifier works.

Cool question!

Very cool question

I am not from Analog background but my analytical ability lead me through to answer it perfectly. Less

### They only ask one technical question about the NMOS transistor: 4V at gate, 5V at drain, open source, then what's the voltage at source.

Source will be at 4V-Vt.

bcz the source is open current Ids is zero, so the transistor is in cutoff region and hence Vgs =0, therefore Vg = Vs Less

if vdvg, source voltage is about (not exatly since it depends on the bulk connection) a voltge between vd and vg (it depends on how far they are from each other because the current value will be different) Less

### How would you draw the CMOS schematic for a 2-input NAND gate? What would the pull-up and pull-down networks look like? If VDD and VSS are switched, what gate is formed?

Buffer

AND. When VDD and VSS are reversed, the NMOSs connected in series becomes the PUN, and parallel PMOSs become the PDN. As long as either of the input is 0, the PDN will conduct, pulling the output to 0. It is only when both inputs are 1 will the PUN conduct, pulling the output to 1. Less

NOR gate

### They asked things like if the source of NMOS is open, what is the voltage at the source if the gate and drain at 3 and 5V. If the gate of inverter is connected through a resistor to a output, what is the output voltage? Also things related to ring oscillator. Mostly just digital stuff, nothing analog like others have said.

The output will be a constant value Vdd/2. As the resistor will force two nodes to be the same since no current flow though. Less

Since there won't be any dc current if the source is open, the source will be at Vg-Vth i.e. 3-vth Less

### How would you size the NMOS and PMOS transistors in an inverter to obtain equal rise and fall times?

pmos size has to more than twice than nmos. thats how you get equal rise and fall time. Less

Depends on the mobility ratio

How was the On Site interview Scheduled? Did you do technical interview first and then behaviorial? How long overall did the on site interview last? Thanks Less

### Give you a disk, 1/4 of the pie is painted black, 3/4 is white. Two detectors which can detect the color (say, when black it output 1, white 0) are 90 degree with each other. Which kind of circuit can be used to detect whether the disk is rotating clockwise or counterclockwise?

Use flip-flop. output of one detector as clock, the other as din.

A tristate PFD