Design engineer Interview Questions in Edinburgh, UK | Glassdoor.co.uk

Design engineer Interview Questions in Edinburgh

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Difference between blocking and non-blocking assignments and when are they used

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Blocking assignment blocks the simulator from executing any other statements. It evaluates the expression on the right of the assignment and updates the left immediately (used in modelling combinational logic) eg. A = B+C Non-blocking assignment evaluates expression on the right of the assignment but does not update the left until the next active edge of the clock. Allows for concurrency since all non-blocking assignments are evaluated concurrently, and update at the next active edge of the clock (used in modelling sequential logic) eg. A <= B+C.

What problem could a rise when crossing from one clock domain to another (different clock speeds), and how could it be fixed?

1 Answer

How do you work under pressure?

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To interpret a drawing and highlight what you note looking at it.

1 Answer

What is setup and hold time.

1 Answer

If a signal does not meet the timing requirements for a flip-flop, how do you make sure you deal with it.

1 Answer

C programming thought process

1 Answer

1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail

Draw a truth table for a basic gate. Then implement it in CMOS.

Typical interview questions were asked and I did not feel it was a challenging interview.