design engineer interview questions shared by candidates
Difference between blocking and non-blocking assignments and when are they used
Blocking assignment blocks the simulator from executing any other statements. It evaluates the expression on the right of the assignment and updates the left immediately (used in modelling combinational logic) eg. A = B+C Non-blocking assignment evaluates expression on the right of the assignment but does not update the left until the next active edge of the clock. Allows for concurrency since all non-blocking assignments are evaluated concurrently, and update at the next active edge of the clock (used in modelling sequential logic) eg. A <= B+C.
1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail