Graduate design engineer Interview Questions in Edinburgh, UK | Glassdoor.co.uk

Graduate design engineer Interview Questions in Edinburgh

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Difference between blocking and non-blocking assignments and when are they used

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Blocking assignment blocks the simulator from executing any other statements. It evaluates the expression on the right of the assignment and updates the left immediately (used in modelling combinational logic) eg. A = B+C Non-blocking assignment evaluates expression on the right of the assignment but does not update the left until the next active edge of the clock. Allows for concurrency since all non-blocking assignments are evaluated concurrently, and update at the next active edge of the clock (used in modelling sequential logic) eg. A <= B+C.

What problem could a rise when crossing from one clock domain to another (different clock speeds), and how could it be fixed?

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If a signal does not meet the timing requirements for a flip-flop, how do you make sure you deal with it.

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C programming thought process

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What is setup and hold time.

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Draw a truth table for a basic gate. Then implement it in CMOS.

For the interview, it is very useful to know logic operations and how logic gates' I/O can be represented by logic operations. It is also very useful to know how certain expressions in verilog are translated into digital circuitry.

Filters and AD/DA conversions. Basic DSP principles. Differences in blocking and non-blocking in system verilog.