I applied online. The process took 1 day. I interviewed at Oracle Engineering Group (Santa Clara, CA) in May 2010
Interview
Interviewed for the ASIC design verification position. Team is very professional and very nice. They ask questions with in the scope of your resume. They asked questions on System Verilog testbenchs, RVM and VMM methodologies, Functional coverage. Few logic design questions like finding a bit pattern in a given stream, FSM coding. Overall the interview process is very friendly.
Interview questions [1]
Question 1
Difference between MOSI and MOESI protocol, and what is Cache coherence?