I applied online. I interviewed at Astranis in Apr 2021
Interview
I applied on their main website, then got an email for an interview. They asked me two technical questions relating to digital logic (CDC) and verilog (writing synthesizable code based on some descriptions).
Interview questions [1]
Question 1
Given you've generated an 80MHz, and 50MHz clock, how do you manage data crossing between these two clock domains?
