I got a call from a staffing agency, saying my interview is scheduled on so and so date and time. However, it was a walkin in some 5 star hotel in which anybody with relevant credentials could apply. In the hotel lobby i was given a blue application form (yellow for verification and pink for firmware {does this mean firmware is more girly? i dont know}). when i filled in the form, two people reviewed it and asked some basic questions like y r u changing the job so early and do you have expierience purely in design etc. When they okayed the form they sent me inside a hall and asked to wait. My interview panelists called me immediately as there were no other canditates waiting for design. Panel consisted of two people, who didn't look like having too much expierience than me. They started with basic project related questions and moved on to digital design fundamental questions.
1) types of reset. Which is more preferable? y? Can you design a simple ckt which asserts reset asynchronously but deasserts synchronously?
2) Setup and hold time related questions. What is the maximum frequency your design can work on? etc.
3) Synchronisation ckt for multi clock domain design. Explain how a two flop arrangement for sync works. What should you do before sending out a signal from one domain to another if its under your control etc.
4) There is a normal 4 bit up counter. Add a combinational logic to the count so that the count will be 0,2,4,6,8,A,C,E,1,3,5,7,9,B,D,F.
5) there is a stream of input coming in. Only if the first bit is 1 in the sequence output 0, else the input should be passed as it is.
6) Explain the FPGA flow. What does translate and map steps do? Should an EDIF file be specific to the device chosen? What does UCF contain and at which step should be input to the flow?
The interview was for around 1 hour. Panelists where very polite and helped out with hints when i got stuck. However, i was not chosen cause i bungled up some basic questions you ought to answer.
