Got Direct Onsite Interview call. The interview was scheduled on Friday in the later half of the day. 3 rounds took place of around 45 minutes each. Was called for another 3+1(Meeting with Director) rounds on Monday as people left early because of being a Friday. First 3 rounds were taken by 1-2 years experienced people. Last 3 rounds by senior Engineers who asked really good questions. Here are the questions asked. People should not panic looking at some questions as most of them were from the projects: 1) What is Flat Placement? 2) Sense Amplifier Working and Schematic 3) How BL got a glitch during read? Ans: Sense Amp’s NMOS driven by BL and BLB with 0.9V and 0.1V gives 2 discharge paths.(Draw yourself and see) 4) Out of NMOS logic on NAND(series NMOS), NOR(Parallel NMOS) and inverter(Single NMOS), which is faster? Which consumes maximum power. 5) Which part of SRAM design consumes the most power? Ans: Read. Bitlines charging and discharging consumes a lot of power and is the reason to cutoff Sense Amp after 100mV to not let bit line drain all down to 0. 6) Pass Transistor circuit voltages at some nodes. 7) Negative Setup and Hold. Can we have both occurring together? 8) Verilog always block with blocking and nonblocking DFF implementation and what hardware they will synthesize by both? 9) Monte-Carlo simulation of 100mV sense Amp differential voltage at worst and best case. 10) What is a Ring Oscillator and what are its applications? 11) What is worst P(Process)? 12) Simulated Annealing Algorithm? What other Algorithm for Placement? 13) SRAM Layout 14) Latch Setup Hold and why don’t we have setup and hold of latch at positive edge? 15) Tristate implementations and which one is better? consider in terms of power 16) SRAM Read waveforms 17) (A+B)C + D implementation and sizing with the inverter sized to 1 and 2 for NMOS and PMOS respectively. 18) What is STA? 19) How you measured the Wirelength in Flat Placement? 20) How you decide the 80mV value for Read Sense Amp? 21) How you assert SAE to get this value? 22) How can you cut off your BL and BLB after sense AMP has read the value to save power. From Senior People: 23) Draw layout of SRAM cell 24) How you size it? 25) How you determine Read and Write SNM. 26) Draw Sense Amplifier schematic that you used. How you assert SA enable signal? How do you determine delta V for SenseAmp? 27) Draw Transistor characteristics and why it is quadratic over the top at saturation? Could it be something else?(He wanted to know the short channel equation) 28) What you did in the ring oscillator project and what were the maximum and minimum operating frequencies? 29) Why pinch off occurs? 30) Find how many times your name occurs in a text file (PERL) 31) Write verilog always block for a DFF and a Dlatch 32) Draw NAND schematic and size it for FO4 33) Do you have any other offer or interview?