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      Nand Memory Datapath Design Engineer Interview

      6 Nov 2021
      Anonymous interview candidate
      Bengaluru
      No offer
      Negative experience
      Difficult interview

      Application

      I applied through a recruiter. The process took 1 day. I interviewed at WD (Bengaluru) in Oct 2021

      Interview

      One Technical interview. Questions are mainly based on CMOS inverter, MOS circuits , Pass transistors, STA, Digital logic Design, Verilog. Questions are based on MOS circuits their voltages. On STA checking for the setup time and hold time violations

      Interview questions [4]

      Question 1

      Draw the CMOS inverter characterstics
      Answer question

      Question 2

      Setup time hold time validation equations
      Answer question

      Question 3

      Design counter circuit
      Answer question

      Question 4

      Fork join in verilog
      Answer question

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