I applied online. The process took 2 months. I interviewed at AMD (Boxborough, MA) in Nov 2018
Interview
2 rounds of phone interviews followed by an onsite interview consisting of 6 rounds. Onsite interviews were interactive and pretty open-ended. The interviewers were looking for optimizations and ideas from the discussions rather than cut to the point answers.
Interview questions [1]
Question 1
Phone screens:
Computer Architecture (Virtual memory, Out of order execution, Hazards in a processor)
Digital Logic (hardware for bit manipulation, synthesis, Verilog constructs)
Programming (OOPS concepts, Data structures)
Onsite:
Logic Design: Verilog coding, Latches, Clock Gating
Programming: OOPS, Perl, hardware modeling
Verification: Verification environment, test plan, coverage
Architecture: Tomasulo Algorithm, Virtual memory
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Interview questions [1]
Question 1
Tell me the difference between combinational and sequential logic
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Interview questions [1]
Question 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?
