AMD Memory PHY RTL engineer interview questions

The interview was fair overall. It began with a brief self‑introduction, followed by questions about the skills listed on my résumé, including UPF, CDC, and RDC. The technical questions were challenging and required a deep understanding of those domains. I was then asked to write Verilog code for clock dividers (divide‑by‑2, divide‑by‑3 with and without a 50% duty cycle). I struggled with this part because I haven’t coded recently and panicked during the exercise. The interviewer did not turn on his camera, which caught me off guard, but he provided honest feedback at the end and informed me that I would not be moving forward. This was my first interview in this field, and I acknowledge that I didn’t perform as well as I could have.