There were 2 Technical rounds, the first round went for 45mins, the interviewer asked me Verilog, System Verilog and UVM based questions, the second round was based on my previous experience, they asked me to explain about my past projects.

There will be usually two rounds of interview & it's quite easy to crack. Basics of SV & UVM is important. Some protocol knowledge is also important. Be thorough on the projects you have worked on.