Ability to provide mentorship and guidance to junior engineers and be an effective team player. Hands-on experience in Synthesis, Floor planning, Placement,……
The role will include driving and optimizing synthesis, power optimization, static timing analysis, and logic verification using an industry-leading SoC design……
Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in……
The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and……
Candidates for this role must be able to access technical data without a requirement for an export license. In this role, you will play a key role in defining……
At least one tapeout in your background, from any node and any company size. Design Reviews: Participate in design reviews and contribute to architecture……
This role will involve cross-functional collaboration to drive product development from NPI through to mass production, with focus on the development, and……
Work with marketing/IC/product teams on competitive analysis and road mapping package technology. Is responsible for road mapping, architecting, design……
Candidates for this role must be able to access technical data without a requirement for an export license. Export control restrictions based upon applicable……
7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs, including ownership of at least one product with……
Execution Model: Help define the operating rhythm, engineering standards, and execution model for the AI team; identify technical risks early and balance model……
Provide pre-sales and post-sales technical support for Synopsys synthesis tools including DC NXT and Fusion Compiler, working directly with customer design……
A technical leader who raises the bar across design quality, performance, and reliability. Maintain deep awareness of advancements in FPGA architectures and……
Translating high-level product and system requirements into scalable digital processing capabilities. Awareness of how digital processing impacts RF system……
Have the unique chance to contribute to cutting-edge GPU products. Work with a team of mathematically focused engineers to design optimal arithmetic hardware……
Farnborough, Hampshire, South East England, England
£25k - £58k (Glassdoor Est.)
Some of the products are part of the next generation radiation hardened satellite modems. Experience with COT/ASIC physical design flow covering: Synthesis,……
PhD welcome but not required; the bar is the work, not the credential. Experience writing microarchitecture specifications and working closely with RTL……
Working closely with colleagues in our manufacturing division, we develop manufacturing and assembly processes and software to deliver quality products by the……
Provide subject-matter expertise during certification reviews, design reviews, and regulator meetings; travel to supplier sites, test labs, and regulator……
Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Deep knowledge of SystemVerilog and UVM.…
Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Deep knowledge of SystemVerilog and UVM.…
The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and……
The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and……
The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and……
Work Location : Cambridge, Bangalore, London, Malaysia, San Jose
Work Expertise : 5 Years - 15 Years
Desired Profile :
Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PD
Experience in Top / Block level ASIC PnR implementation (RTL to GDSII).
Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
Excellent communication and presentation skills, experience in collaborating with global teams.
Experience in hierarchical designs and/or Low Power implementation is an advantage.
Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
Ability to provide mentorship and guidance to junior engineers and be an effective team player.
Expertise in Cadence Innovus, Tempus, Calibre
Required relevant expertise for India and Malaysia is 5+ years and 10+ years of relevant expertise for other locations
VISA SPONSORED FOR MALAYSIA
Base pay range
The minimum salary is £37k and the max salary is £50k.
£37k – £50k/yr (Glassdoor Est.)
£43k
/yr Median
Cambridge, East of England, England
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