Key Responsibilities:

• Design, implement, and maintain embedded firmware for DSP cores and MCUs (RISC V and/or Arm).
• Build and optimize real-time signal-processing pipelines (fixed-point and/or floating-point), potentially including FFTs, filters, modulation/demodulation, codecs, feature extraction, or control loops.
• Develop firmware using a mix of C/C++ (and selective assembly where appropriate), with strong focus on performance, memory, and power optimization.
• Work with SoC/board peripherals: DMA, timers, SPI, I²C, UART, I²S/TDM, PWM, GPIO, and relevant bus fabrics.
• Bring up new hardware: boot flows, clocks, memory maps, interrupt vectors, peripheral init, and early validation.
• Implement and debug drivers and RTOS components (e.g., Zephyr or equivalent), including task scheduling, synchronization primitives, and ISR design.
• Develop test strategies: unit tests, hardware-in-the-loop tests, test automation, and manufacturing/production diagnostics.
• Use debugging/profiling tools: JTAG/SWD, logic analyzers, oscilloscopes, trace (ETM/ITM), and cycle-accurate profiling when available.
• Collaborate cross-functionally with hardware, FPGA/ASIC, systems, and application teams to define requirements and interfaces.
• Contribute documentation: architecture notes, interface specs, timing budgets, work packages, and bring-up guides.
• Participate in code reviews and help establish best practices for embedded quality, safety, and maintainability.

Required Skills and Qualifications:

• Strong professional experience developing embedded firmware in C/C++ for MCUs and/or DSPs.
• Hands-on experience with RISC V and/or Arm architecture (Cortex M/A), including interrupts, memory, caches, and performance characteristics.
• Solid understanding of embedded software fundamentals:
• register-level programming, memory-mapped I/O
• concurrency (ISRs, RTOS tasks), race conditions, timing determinism
• fixed-point arithmetic, numerical precision, and overflow/underflow management
• Proven ability to optimize firmware: cycle counting, memory layout, DMA usage, cache behavior, minimizing latency and jitter.
• Comfortable with toolchains and build systems:
• GCC/LLVM-based toolchains, cross-compilation
• CMake/Make, Meson, linker scripts, map files
• Strong debugging skills with hardware and firmware:
• JTAG/SWD debugging
• root-cause analysis of timing and performance issues
• Source control expertise (Git) and disciplined engineering practices (code reviews, CI).

Preferred Skills and Qualifications:

• Languages: C, C++, (optional) assembly, Python for test tooling/scripts
• Architectures: RISC V, Arm Cortex M/A, DSP cores
• RTOS/OS: Zephyr, embedded Linux (optional)
• Tools: JTAG/SWD debuggers, GDB, OpenOCD/J-Link, logic analyzer, oscilloscope, trace tools
• Practices: profiling, timing analysis, unit/integration testing, CI/CD for embedded
• Experience with common DSP libraries/techniques (e.g., CMSIS-DSP, vendor DSP libs) and SIMD/vector optimization patterns.
• Experience with Zephyr, or embedded Linux on Arm.
• Familiarity with bootloaders, secure boot, OTA update mechanisms, and field diagnostics.
• Understanding of digital communications, or audio, processing domains.
• Exposure to safety/security standards (e.g., MISRA C/C++, IEC 61508, ISO 26262)